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U.S. Patents Awarded to Inventors in Oregon (July 22)
[July 22, 2014]

U.S. Patents Awarded to Inventors in Oregon (July 22)


(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., July 22 -- The following federal patents were awarded to inventors in Oregon.

*** Intel Assigned Patent for PCI Express Tunneling Over Multi-protocol I/O Interconnect ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,782,321) developed by David J. Harriman, Portland, Oregon, and Maxim Dan, Haifa, Israel, for "PCI express tunneling over a multi-protocol I/O interconnect." The patent application was filed on Feb. 8, 2012 (13/369,140). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=87,82,321.PN.&OS=PN/87,82,321&RS=PN/87,82,321 Written by Sudarshan Harpal; edited by Jaya Anand.



*** Intel Assigned Patent for Dynamic and Idle Power Reduction Sequence Using Recombinant Clock and Power Gating ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,782,456) developed by five co-inventors for "dynamic and idle power reduction sequence using recombinant clock and power gating." The co-inventors are Sin S. Tan, Portland, Oregon, Srikanth T. Srinivasan, Portland, Oregon, Sivakumar Radhakrishnan, Portland, Oregon, Stephan J. Jourdan, Portland, Oregon, and Lily Pao Looi, Portland, Oregon.

The patent application was filed on Dec. 24, 2010 (12/978,452). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,782,456.PN.&OS=PN/8,782,456&RS=PN/8,782,456 Written by Kusum Sangma; edited by Jaya Anand.


*** Sensory Assigned Patent ALEXANDRIA, Va., July 22 -- Sensory, Santa Clara, California, has been assigned a patent (8,781,825) developed by four co-inventors for "reducing false positives in speech recognition systems." The co-inventors are Jonathan Shaw, Oregon City, Oregon, Pieter Vermeulen, Portland, Oregon, Stephen Sutton, Portland, Oregon, and Robert Savoie, Los Altos, California.

The patent application was filed on Aug. 24, 2011 (13/217,134). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=87,81,825.PN.&OS=PN/87,81,825&RS=PN/87,81,825 Written by Balkishan Dalai; edited by Jaya Anand.

*** Intel Assigned Patent for Secure User Presence Detection and Authentication ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,782,398) developed by Mojtaba Mojy Mirashrafi, Portland, Oregon, Mousumi Hazra, Beaverton, Oregon, and Gyan Prakash, Beaverton, Oregon, for a "secure user presence detection and authentication." The patent application was filed on June 26, 2012 (13/533,449). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,782,398.PN.&OS=PN/8,782,398&RS=PN/8,782,398 Written by Kusum Sangma; edited by Jaya Anand.

*** Intel Assigned Patent ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,782,382) developed by four co-inventors for "last branch record indicators for transactional memory." The co-inventors are Ravi Rajwar, Portland, Oregon, Peter Lachner, Heroldstatt, Germany, Laura A. Knauth, Portland, Oregon, and Konrad K. Lai, Vancouver, Washington.

The patent application was filed on March 6, 2013 (13/786,724). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=87,82,382.PN.&OS=PN/87,82,382&RS=PN/87,82,382 Written by Sudarshan Harpal; edited by Jaya Anand.

*** Intel Assigned Patent for Processor to Execute Shift Right Merge Instructions ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,782,377) developed by four co-inventors for a "processor to execute shift right merge instructions." The co-inventors are Julien Sebot, Hillsboro, Oregon, William W. Macy, Palo Alto, California, Eric Debes, Santa Clara, California, and Huy V. Nguyen, Pflugerville, Texas.

The patent application was filed on May 22, 2012 (13/477,544). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=87,82,377.PN.&OS=PN/87,82,377&RS=PN/87,82,377 Written by Sudarshan Harpal; edited by Jaya Anand.

*** Intel Assigned Patent for Methods and Tools to Debug Complex Multi-core, Multi-socket QPI Based System ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,782,468) developed by Binata Bhattacharyya, Bangalore, India, Jayakrishna Guddeti, Bangalore, India, and Keshavan K. Tiruvallur, Tigard, Oregon, for "methods and tools to debug complex multi-core, multi-socket QPI based system." The patent application was filed on Dec. 21, 2011 (13/333,952). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,782,468.PN.&OS=PN/8,782,468&RS=PN/8,782,468 Written by Kusum Sangma; edited by Jaya Anand.

*** Cadence Design Systems Assigned Patent ALEXANDRIA, Va., July 22 -- Cadence Design Systems, San Jose, California, has been assigned a patent (8,782,577) developed by five co-inventors for a "method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness." The co-inventors are Ed Fischer, Salem, Oregon, David White, San Jose, California, Michael McSherry, Portland, Oregon, Bruce Yanagida, Snohomish, Washington, and Vance Kenzle, San Jose, California.

The patent application was filed on Dec. 30, 2010 (12/982,822). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,782,577.PN.&OS=PN/8,782,577&RS=PN/8,782,577 Written by Kusum Sangma; edited by Jaya Anand.

*** Intel Assigned Patent for Liner Layers for Metal Interconnects ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,779,589) developed by four co-inventors for "[l]iner layers for metal interconnects." The co-inventors are Sadasivan Shankar, Cupertino, California, Michael G. Haverty, Mountain View, California, and Daniel J. Zierath, Portland, Oregon.

The patent application was filed on Dec. 20, 2010 (12/973,773). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8779589.PN.&OS=PN/8779589&RS=PN/8779589 Written by Jude Bautista, edited by Vessie Ann Abalos.

*** Intel Assigned Patent for Managing Non-voice Emergency Services in Wireless Communication Network ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,781,438) developed by Eric Siow, Beaverton, Oregon, Muthaiah Venkatachalam, Beaverton, Oregon, and Puneet K. Jain, Hillsboro, Oregon, for "managing non-voice emergency services in a wireless communication network." The patent application was filed on Nov. 21, 2012 (13/684,131). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,781,438.PN.&OS=PN/8,781,438&RS=PN/8,781,438 Written by Balkishan Dalai; edited by Jaya Anand.

*** Intel Assigned Patent for Adaptive Polling for Bursty Wireless Data Traffic ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,780,881) developed by Muthaiah Venkatachalam, Beaverton, Oregon, Chun Nie, Hillsboro, Oregon, and Xiangying Yang, Portland, Oregon, for an "adaptive polling for bursty wireless data traffic." The patent application was filed on Dec. 21, 2006 (11/644,469). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,780,881.PN.&OS=PN/8,780,881&RS=PN/8,780,881 Written by Deviprasad Jena; edited by Jaya Anand.

*** Intel Assigned Patent ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,781,641) developed by four co-inventors for a "method and apparatus for external processor thermal control." The co-inventors are Eric C. Samson, Folsom, California, John William Horigan, Mountain View, California, Robert T. Jackson, San Jose, California, and Ticky Thakkar, Portland, Oregon.

The patent application was filed on Dec. 29, 2010 (12/980,648). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=87,81,641.PN.&OS=PN/87,81,641&RS=PN/87,81,641 Written by Balkishan Dalai; edited by Jaya Anand.

*** Intel Assigned Patent for Optimized Fast Hessian Matrix Computation Architecture ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,781,234) developed by five co-inventors for an "optimized fast hessian matrix computation architecture." The co-inventors are Yong Zhang, Hillsboro, Oregon, Ravishankar Iyer, Portland, Oregon, Rameshkumar G. Illikkal, Portland, Oregon, Donald K. Newell, Portland, Oregon, and Jianping Zhou, Fremont, California.

The patent application was filed on Oct. 1, 2010 (12/896,077). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,781,234.PN.&OS=PN/8,781,234&RS=PN/8,781,234 Written by Balkishan Dalai; edited by Jaya Anand.

*** Intel Assigned Patent for Enhanced Privacy ID Based Platform Attestation ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,782,401) developed by Nitin V. Sarangdhar, Portland, Oregon, and Daniel Nemiroff, Folsom, California, for the "enhanced privacy ID based platform attestation." The patent application was filed on Sept. 26, 2012 (13/627,784). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,782,401.PN.&OS=PN/8,782,401&RS=PN/8,782,401 Written by Kusum Sangma; edited by Jaya Anand.

*** Intel Assigned Patent for Techniques to Wirelessly Transmit Data ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,781,447) developed by four co-inventors for the "techniques to wirelessly transmit data." The co-inventors are Barry A. O'Mahony, Banks, Oregon, Jeffrey R. Foerster, Portland, Oregon, V. Srinivasa Somayazulu, Portland, Oregon, and Ozgur Oyman, San Jose, California.

The patent application was filed on Sept. 24, 2010 (12/889,625). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,781,447.PN.&OS=PN/8,781,447&RS=PN/8,781,447 Written by Balkishan Dalai; edited by Jaya Anand.

*** University of Southern California Assigned Patent ALEXANDRIA, Va., July 22 -- University of Southern California, Los Angeles, has been assigned a patent (8,778,716) developed by four co-inventors for "integrated circuits based on aligned nanotubes." The co-inventors are Chuan Wang, Albany, California, Koungmin Ryu, Los Angeles, Chongwu Zhou, San Marino, California, and Alexander Badmaev, Hillsboro, Oregon.

The patent application was filed on Jan. 14, 2013 (13/740,955). The full text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8778716.PN.&OS=PN/8778716&RS=PN/8778716 Written by Eloisa Asedillo; edited by Vessie Ann Abalos.

*** USGI Medical Assigned Patent for Laparoscopic Hernia Repair ALEXANDRIA, Va., July 22 -- USGI Medical, San Clemente, California, has been assigned a patent (8,777,965) developed by four co-inventors for devices and methods "for laparoscopic hernia repair." The co-inventors are Eugene G. Chen, Carlsbad, California, Tracy D. Maahs, Yorba Linda, California, Richard C. Ewers, Fullerton, California, and Lee L. Swanstrom, Portland, Oregon.

The patent application was filed on May 9, 2011 (13/103,936). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8777965.PN.&OS=PN/8777965&RS=PN/8777965 Written by Marlyn Vitin.

*** Intel Assigned Patent for Audio/video Streaming in Topology of Devices ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,782,237) developed by Srikanth Kambhatla, Portland, Oregon, for the "audio/video streaming in a topology of devices." The patent application was filed on May 5, 2010 (12/774,023). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=87,82,237.PN.&OS=PN/87,82,237&RS=PN/87,82,237 Written by Sudarshan Harpal; edited by Jaya Anand.

*** Intel Assigned Patent for Enhanced Dislocation Stress Transistor ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,779,477) developed by five co-inventors for "[e]nhanced dislocation stress transistor." The co-inventors are Hemant Deshpande, Beaverton, Oregon, Cory Weber, Hillsboro, Oregon, Daniel B. Aubertine, North Plains, Oregon, Anand Murthy, Portland, Oregon, and Mark Liu, West Linn, Oregon.

The patent application was filed on Aug. 14, 2008 (12/191,814). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8779477.PN.&OS=PN/8779477&RS=PN/8779477 Written by Jude Bautista, edited by Vessie Ann Abalos.

*** Intel Assigned Patent for Method for Associating Program Execution Sequences ALEXANDRIA, Va., July 22 -- Intel, Santa Clara, California, has been assigned a patent (8,782,629) developed by Mingqiu Sun, Beaverton, Oregon, for "associating program execution sequences with performance counter events." The patent application was filed on June 29, 2005 (11/172,130). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=87,82,629.PN.&OS=PN/87,82,629&RS=PN/87,82,629 Written by Amal Ahmed; edited by Jaya Anand.

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